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Computer architecture : a quantitative approach/ by John L. Hennessy, and David A. Patterson

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cambridge : Morgan Kaufmann Publishers, 2019.Edition: 6th editionDescription: xxix, 617, A-55, B-67, C-78, R-36, I-48 p. ; 24 cm. PBISBN:
  • 9789351073659
Subject(s): DDC classification:
  • 004.22 HEN
Contents:
Fundamentals of quantitative design and analysis Memory hierarchy design Instruction-level parallelism and its exploitation Data-level parallelism in vector, SIMD, and GPU architectures Thread-level parallelism Warehouse-scale computers to exploit request-level and data-level parallelism Domain-specific architectures Appendix A. Instruction set principles ; Appendix B. Review of memory hierarchy ; Appendix C. Pipelining : basic and intermediate concepts Online appendices. Appendix D. Storage systems ; Appendix E. Embedded systems ; Appendix F. Interconnection networks ; Appendix G. Vector processors in more depth ; Appendix H. Hardware and software for VLIW and EPIC ; Appendix I. Large-scale multiprocessors and scientific applications ; Appendix J. Computer arithmetic ; Appendix K. Survey of instruction set architectures ; Appendix L. Advanced concepts on address translation ; Appendix M. Historical perspectives and references
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Item type Current library Collection Call number Status Barcode
Book Book Ranganathan Library Computer Science and Technology 004.22 HEN (Browse shelf(Opens below)) Available 050393

Fundamentals of quantitative design and analysis
Memory hierarchy design
Instruction-level parallelism and its exploitation
Data-level parallelism in vector, SIMD, and GPU architectures
Thread-level parallelism
Warehouse-scale computers to exploit request-level and data-level parallelism
Domain-specific architectures
Appendix A. Instruction set principles ; Appendix B. Review of memory hierarchy ; Appendix C. Pipelining : basic and intermediate concepts
Online appendices. Appendix D. Storage systems ; Appendix E. Embedded systems ; Appendix F. Interconnection networks ; Appendix G. Vector processors in more depth ; Appendix H. Hardware and software for VLIW and EPIC ; Appendix I. Large-scale multiprocessors and scientific applications ; Appendix J. Computer arithmetic ; Appendix K. Survey of instruction set architectures ; Appendix L. Advanced concepts on address translation ; Appendix M. Historical perspectives and references

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