000			01743nam a22002537a 4500
003			IN-BdCUP
005			20240430111335.0
008			240430b ii ||||| |||| 00| 0 eng d
020			_a9789351073659
040			_beng _cIN-BdCUP
041			_aeng
082			_a004.22 _bHEN
100			_aHennessy, John L. _eAuthor
245			_aComputer architecture : _ba quantitative approach/ _cby John L. Hennessy, and David A. Patterson
250			_a6th edition.
260			_aCambridge : _bMorgan Kaufmann Publishers, _c2019.
300			_a xxix, 617, A-55, B-67, C-78, R-36, I-48 p. ; _c24 cm. _fPB
505			_aFundamentals of quantitative design and analysis Memory hierarchy design Instruction-level parallelism and its exploitation Data-level parallelism in vector, SIMD, and GPU architectures Thread-level parallelism Warehouse-scale computers to exploit request-level and data-level parallelism Domain-specific architectures Appendix A. Instruction set principles ; Appendix B. Review of memory hierarchy ; Appendix C. Pipelining : basic and intermediate concepts Online appendices. Appendix D. Storage systems ; Appendix E. Embedded systems ; Appendix F. Interconnection networks ; Appendix G. Vector processors in more depth ; Appendix H. Hardware and software for VLIW and EPIC ; Appendix I. Large-scale multiprocessors and scientific applications ; Appendix J. Computer arithmetic ; Appendix K. Survey of instruction set architectures ; Appendix L. Advanced concepts on address translation ; Appendix M. Historical perspectives and references
650			_a Computer architecture
650			_aComputers and IT
650			_aOrdinateurs Architecture
700			_aPatterson, David A. _eAuthor
942			_2ddc _cBK _n0
999			_c52186 _d52186